发明名称 MASK ALIGNING METHOD FOR SEMICONDUCTOR DEVICE
摘要 PURPOSE:To minimize the misalignment of the masks between both of the N-type emitter of an N-P-N transistor and the P-type emitter of a P-N-P type transistor and contact windows by using a photomask having the same number of the same or similar figures as a plurality of other same figures on a substrate, and performing mask alignment. CONSTITUTION:A plurality of the same figures are formed on a semiconductor substrate in different steps. Mask alignment is performed for said figures by using a photomask having the figures whose shapes are the same as or similar to the shapes of said figures on the substrate. The number of the figures on the photomask is the same as that of the figures on the substrate. For example, when the P-type emitter of a P-N-P transistor is formed, an aligning mark 2a for forming the P-type emitter of the P-N-P transistor is formed at a place neighboring an aligning mark 1a which is provided when the N-type emitter of the N-P-N transistor is provided on the semiconductor substrate. After a specified diffusing step, the mask alignment is performed so that aligning marks 3a provided on the photomask in a contact-window forming step are aligned with the centers of said aligning marks 1a and 2a on the semiconductor substrate.
申请公布号 JPH02213117(A) 申请公布日期 1990.08.24
申请号 JP19890034010 申请日期 1989.02.14
申请人 MATSUSHITA ELECTRON CORP 发明人 NISHIMURA HISAHARU
分类号 G03F9/00;H01L21/027;H01L21/30 主分类号 G03F9/00
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