摘要 |
The circuit multiplies an analog input value (1) by a digital input value (16). It uses a dual slope process for an A/D converter with an integrator (4 - 7), a comparator (8), a control (9 - 11, 2, 3), a clock pulse generator (14), a result counter (13), and a measuring period counter (12). The measuring period counter is adjustable by the digital input value. Pref. a memory (19), which can be loaded with the digital input value, is coupled to the adjusting input of the measuring period counter. The memory may contain several, preset memory contents, selectable by the digital input value. ADVANTAGE - Low-cost design for digital sensitivity compensation.
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申请人 |
SIEMENS AG, 1000 BERLIN UND 8000 MUENCHEN, DE |
发明人 |
REINER, ROBERT, DIPL.-ING., 8014 NEUBIBERG, DE |