发明名称 Analog input multiplying circuit for A=D converter - has measuring period counter, adjustable by digital input values
摘要 The circuit multiplies an analog input value (1) by a digital input value (16). It uses a dual slope process for an A/D converter with an integrator (4 - 7), a comparator (8), a control (9 - 11, 2, 3), a clock pulse generator (14), a result counter (13), and a measuring period counter (12). The measuring period counter is adjustable by the digital input value. Pref. a memory (19), which can be loaded with the digital input value, is coupled to the adjusting input of the measuring period counter. The memory may contain several, preset memory contents, selectable by the digital input value. ADVANTAGE - Low-cost design for digital sensitivity compensation.
申请公布号 DE3937869(A1) 申请公布日期 1990.08.23
申请号 DE19893937869 申请日期 1989.11.14
申请人 SIEMENS AG, 1000 BERLIN UND 8000 MUENCHEN, DE 发明人 REINER, ROBERT, DIPL.-ING., 8014 NEUBIBERG, DE
分类号 G01D3/02;G06J1/00 主分类号 G01D3/02
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