| 摘要 |
There are provided a controller for an instruction cache and an instruction TLB (Translation Look-aside Buffer), and a method of controlling the same. The controller includes: a processor core outputting an address of a current instruction; a branch predictor performing a branch prediction of the outputted current instruction address to output a final branch prediction value; a branch target buffer predicting a branch target address of the outputted current instruction address at the same time of the branch prediction of the branch predictor, to output a prediction target address; and an address selection unit selecting and outputting one of the prediction target address and the current instruction address where a branch prediction result is not "taken", wherein the branch prediction and the branch target address prediction for the current instruction address are initiated, on the assumption that a previous instruction of the current instruction is not a branch instruction, before a branch prediction and a branch target address prediction for an address of the previous instruction are ended, and wherein the address outputted from the address selection unit wakes-up corresponding cache lines of the instruction cache and the instruction TLB, which use a dynamic voltage scaling. |
