发明名称 HEURISTIC PROCESSOR
摘要 <p>A heuristic processor (10) incorporates a digital arithmetic unit (16) arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centres, and to transform the squared norms in accordance with a nonlinear function to produce training ζ vectors. A systolic array (18/20) arranged for QR decomposition and least means squares processing forms combinations of the elements of each ζ vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed test data to provide estimates of unknown results. The processor (10) is applicable to provide estimated results for problems which are nonlinear and for which explicit mathematical formalisms are unknown.</p>
申请公布号 WO1990009643(A1) 申请公布日期 1990.08.23
申请号 GB1990000142 申请日期 1990.01.31
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