发明名称 FAULT MASKING IN SEMICONDUCTOR MEMORIES
摘要 <p>A random access memory device with a memory addressable by row and column is addressed by a source of binary addresses defining a linear address space via row and column decoders responsive to respective groups of bits from the address source to address individual rows and columns respectively of the memory. The bits are permuted between the address source and the decoders so that at least the higher order bits from the address source are applied to row and column decoders alternately. The memory is thus accessed in rectangular blocks, called tiles, which, by virtue of the interleaving of bits are arranged in a tiling pattern shifting alternately in the row direction and the column direction.</p>
申请公布号 WO1990009634(A1) 申请公布日期 1990.08.23
申请号 GB1990000228 申请日期 1990.02.13
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址