| 摘要 |
<p>A DRAM controller comprises an address output controller (30) for transferring an address-designating signal to a dynamic RAM, a data output controller (32, 34, 36) for transferring data to be written into and read-out from that memory region of the dynamic RAM which is designated by the address-designating signal, and a control circuit responsive to a mode-designating signal for generating various control signals corresponding to an access mode of the dynamic RAM designated by the mode-designating signal, and supplying the control signals to the dynamic RAM, address output controller (30), and data output controller (32, 34, 36) in a predetermined sequence. In the DRAM controller, the control circuit includes a signal-generating unit (50B) for generating the control signals in a specific access mode which requires an access time longer than the machine cycle of a processor for generating the address-designating signal, the data to be written, and the mode-designating signal, and for delaying the generating of the control signals every time the designation of the specific access mode is repeated. <IMAGE></p> |
