发明名称 PHASE ADJUSTING CIRCUIT
摘要 PURPOSE:To eliminate the need for a circuit to regenerate a main clock from a 1/2 period clock and to avoid the deterioration in the picture quality by providing a delay device separately as a 1st delay device for coarse adjustment and a 2nd delay device for fine adjustment. CONSTITUTION:The delay device is provided separately as a 1/2 period delay device 33 for coarse adjustment and a 1/2 period delay device 37 for fine adjustment. With a switch 32 thrown to the position of a D input terminal, a main clock 14 is inputted to a 4th FF 31, and with the switch 32 thrown to the position of an E input terminal, a 1/2 period delay main clock 14 is inputted to the 4th FF 31. Moreover, a clock 36 outputted from a switch 32 is inputted to a delay device 37, the phase within a 1/2 period is set and a retarded clock 38 is fed to a 5th FF 39. Then an output data 41 from the FF 31 is latched in an FF 39, and a phase within one sampling period is set optionally to a digital data 42. Thus, the circuit constitution is simplified and the deterioration in the picture quality is eliminated.
申请公布号 JPH02210908(A) 申请公布日期 1990.08.22
申请号 JP19890029625 申请日期 1989.02.10
申请人 NEC CORP 发明人 SHIKINA TOMOYOSHI
分类号 H03K5/133;H03K5/13;H03K5/135;H04N7/24;H04N19/00;H04N19/59 主分类号 H03K5/133
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