| 摘要 |
PURPOSE:To decrease the number of full adders and increasing the computing speed for addition of complements of 2 without increasing the circuit area by providing an inverter to invert the carry signal received from a lower rank of an adder to which an MSB of an input signal is inputted as well as the addition output of the adder. CONSTITUTION:The logical arithmetic of a code bit process is checked and the polarities of A0 - A3 and B0 - B3 of the input data are operated via a circuit equal to a full adder. Thus code bits of the output signals and the (MSB - 1)-th bit addition output are obtained via the full adders 11 - 14 equal to the number of input data. In other words, an inverter 15 is set between adders 13 and 14 together with an inverter 16 added to the addition output of the adder 14. As a result, a processor for complement code of 2 can be obtained with the circuits 11 - 14 equal to the number of input bits in case the processor is produced with a semiconductor integrated circuit. Thus it is possible to reduce the circuit area and to increase the computing speed. |
