| 摘要 |
PURPOSE:To arbitrarily set the selection period of a matrix circuit irrespective of a period of a clock signal by inputting clock signals whose phases only are different to a first and a second shift registers, respectively, and supplying plural signals outputted from a level shifter to the first and the second electrode groups of the matrix circuit as driving signals, respectively. CONSTITUTION:In the first or the second shift register 1, 2, a clock signal for determining a selection start timing in the selection period of a matrix circuit, and a clock signal for determining a selection end timing in the same selection period are inputted to one of them and the other, respectively. Also, plural logic circuits 3 execute the logical operation of outputs of the shift registers 1, 2, and a level shifter 4 converts the voltage levels of each signal outputted from each logic circuit 3, respectively. Accordingly, the pulse width of a driving signal outputted from the level shifter 4 can be set freely by changing the phase of the clock signal inputted to the shift registers 1, 2. In such a manner, the selection period of the matrix circuit can be arbitrarily set. |
