| 摘要 |
<p num="1"><br/><br/> SYSTEM FOR GENERATING MASK PATTERN FOR<br/><br/> VECTOR DATA PROCESSOR<br/><br/><br/> ABSTRACT OF THE DISCLOSURE<br/><br/><br/> A system for generating a mask pattern for a vector<br/>data processor having at least a mask register and a<br/>vector register in which, when the value of the mask<br/>register is "1", a calculation is executed for the<br/>corresponding element of the vector register, and when<br/>the value of the mask register is "0", a calculation is<br/>not executed, in accordance with the so-called calcula-<br/>tional mask function. The system includes a designation<br/>unit for designating sequential i elements of "0" or "1"<br/>from the head element of the mask register and the<br/>subsequent sequential j elements of "1" or "0", and a<br/>control unit for rendering the i elements to be "0"<br/>or "1", the j elements to be "1" or "0", and the remain-<br/>ing entire elements to be all "0''s" or all 1''s, when "i"<br/>plus "j" is smaller than a vector length which is the<br/>object of calculation of a vector data operand for use<br/>in a vector instruction, and a desired mask pattern of<br/> "0" or ''1" is able to be generated in the mask register.<br/> |
