发明名称 Parallel computer with distributed shared memories and distributed task activating circuits
摘要 In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.
申请公布号 US4951193(A) 申请公布日期 1990.08.21
申请号 US19870085646 申请日期 1987.08.14
申请人 HITACHI, LTD. 发明人 MURAMATSU, AKIRA;SAKODA, KOUSUKE;YOSHIHARA, IKUO;NAKAO, KAZUO;NOHMI, MAKOTO;HAMANAKA, NAOKI;NAGASHIMA, SHIGEO;TANAKA, TERUO
分类号 G06F9/45;G06F9/50 主分类号 G06F9/45
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