| 摘要 |
PURPOSE:To reduce the access frequency and arithmetic frequency of a CPU and to improve a processing speed accompanied with a data movement by designating only a necessary bit, reading it and erasing it at the time of moving the data developed to a bit image. CONSTITUTION:For a timing generating circuit 1, by making a latch signal 22 and an output enable signal 19 into 'L' level, the data are set to a latch circuit 4, and simultaneously, the information is outputted to a data bus 12. Namely, to the data bus 12, the data of a RAM 2 are outputted only as to the bit in which '1' is set to a latch circuit 5. According to mask bit information set to the latch circuit 5, only the designated bit is read, and simultaneously, the data of the corresponding bit in the RAM 2 are cleared. Thus, the speedy data processing can be executed. |
