| 摘要 |
An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the target and delay signal paths. The variable delay module is operable to delay a first clock signal on the delay path so that a bias input signal presented to the delay bias input, when a bias input signal is present, corresponds to the time delay between the first clock signal and a second clock signal on the target signal path.
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