| 摘要 |
<p>PURPOSE:To attain clock extraction with less jitter and less amplitude fluctuation by interpolating the pulse missing part of a pulse train signal inputted to a tank circuit. CONSTITUTION:A pulse train signal (d) is inputted to the delay circuit 21 of an interpolation section 20 and one input terminal of an OR circuit 22. The delay circuit 21 retards the pulse train signal (d) by a half period to output a delay signal (e). The delay signal (e) is inputted to other input terminal of the OR circuit 22. A pulse train signal (f) is the result of interpolating the pulse train signal (d) by inserting a pulse 103 to the pulse missing part and composed of pulses arranged regularly. The 2nd pulse train signal (f) is inputted to a tank circuit 30. The tank 30 outputs a clock signal (g), f0 in the frequency and AP-P in the level respectively based on the pulse train signal (f).</p> |
