| 摘要 |
PURPOSE:To prevent an output clock signal from generating disturbance even at system switching by resetting a frequency divider circuit frequency-dividing an input clock signal with a selected phase locking clock signal so as to make the phases of phase locking clock signals of two systems coincident with each other. CONSTITUTION:Singles being the result of differentiating output signals B, E from 2 systems of frequency divider circuits 3, 4 at differentiating circuits 5, 6 respectively are inputted to a selection circuit 7 as phase locking clock signals C, F, a selected phase locking clock signal H is used as a reference signal to a phase comparator 9 and the signal H is used to reset 2 systems of the frequency divider circuits 3, 4. The output phase of the frequency divider circuits 3, 4 is set properly at the reset of the frequency divider circuits to make the phase of the phase locking clock signals C, F for the two systems inputted to the selection circuit 7 coincident with each other. Thus, there is no phase change exists in the reference signal to the phase comparator 9 even at the switching of the phase locking clock signal and of disturbance takes place in the output clock signal. |
