| 摘要 |
<p>Disclosed is a circuit for testability to be provided in a logic circuit comprising a plurality of functional groups which are respectively composed of a plurality of register groups (100 to 107) respectively comprising a plurality of resisters having the same functions. The circuit for testability is characterized by composition in which each the register group (100 to 107) is corresponding to each scan path (SP100 to SP107), and each the scan path (SP100 to SP107) is selected by an address decoder (118), further each the register group (100 to 107) carries out input and output of data to bus lines (IB0 to IB7) through the corresponding scan path (SP100 to SP107), whereby register groups can be divided so as to separate tests on an internal logic circuit of the functional blocks (22, 24) and tests on a logic circuit related to I/O signals of the functional blocks (22, 24). Further disclosed is another circuit for testability characterized by composition in which scan paths respectively corresponding to register groups (100 to 107) which are inputted test data and those outputted test data in functional blocks (22, 24) as objects in the tests are connected to the same bus lines, whereby the number of the bus lines to be required can be reduced.</p> |
