Method and means for error checking of dram-control signals between system modules.

摘要

For the detection of errors in DRAM-control signals transmitted across an interconnect between system modules, a comparison of the parity of the control signals as transmitted and as received is performed at the transmitter module. The transmitter module is provided with a parity generator for determining the parity of the control signals being transmitted. The receiver module is provided with a similar parity generator for determining the parity of the control signals as received from the interconnect. The receiver module generates a parity signal indicating the parity determined by the parity generator in the receiver module, and transmits the parity signal over the interconnect to the transmitter module. At the transmitter module, the parity indicated by the parity signal is compared with the parity determined by the parity generator in the transmitter module for generating an error signal when the parity indicated by the parity signal is unequal to the parity determined by the parity generator in the transmitter module. Preferably one of the DRAM-control signals is used as a time reference for determining the point at which the parity signal from the receiver module is compared to the parity determined for previously transmitted control signals. A delay of a predetermined period of time is provided between the time that the control signals are transmitted from the transmitter module and the point at which the comparison of parity signals is performed: this predefined delay is based upon the time required for signals to traverse, in both directions, the path through the interconnection between the transmitter module and the receiver module, as well as the clock skews inherent in the modules.