| 摘要 |
<p>A clock signal conversion circuit which receives a clock signal (Ecp) and a control signal (Ct) and generates a converted clock signal (Icp), said clock signal conversion circuit comprising: means (12) for holding said control signal (Ct) in response to said clock signal (Ecp) and outputting a held control signal (Sa); means (13) for selectively masking said clock signal (Ecp) in response to said held control signal (Sa) and outputting said converted clock signal (Icp); and means (11) for generating a set signal (Sc) in response to said clock signal (Ecp), said control signal (Ct) and said held control signal (Sa, Sb), said holding means (12) being forced to assume a predetermined state in response to said set signal (Sc).</p> |
