| 摘要 |
A PWM inverter in which high-surge voltage is not applied across terminals of a switching device thereof is provided by preventing multi-phase simultaneous switching. A multi-phase simultaneous-switching prevention circuit ( 100 ) that includes: a plurality of input means each for taking in, as an input signal, one of multi-phase control signals outputted from a PWM signal generating circuit; blocking pulse generating means each for generating a blocking pulse, for a predetermined period, in synch with the rising or the falling of the input signal of one phase, in order to block the rising or the falling of the input signals of the other phases; blocking signal forming means each for outputting a blocking signal whose blocking period is made to be the width of a pulse formed by the logical sum of a plurality of the other-phase blocking pulses from the blocking pulse generating means; signal blocking means each for receiving the input signal of the one phase, and outputting a signal whose rising or falling is delayed until the end of the blocking period; and a plurality of output means each for outputting to the exterior of the prevention circuit the output signal from the signal blocking means, is inserted across a gate driving circuit ( 3 ), and a three-phase PWM signal generating circuit ( 1 ).
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