ANWEISUNGSEINRICHTUNG UND VERFAHREN ZUM PIPELINE-LADEN VON DATEN IN EINEN PROZESSOR

摘要

A microprocessor having a pipelined architecture, an onchip data cache 70, a floating-point unit, a floating-point data latch 78 and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction handler comprises a first-in-first-out memory 65 for accumulating data in a pipeline manner, a first circuit means 60, 62 for coupling data from the external bus to the first-in-first-out memory and a second circuit means 67, 69, 74, 75 for transferring the data stored in the first-in-first-out memory to the floating-point data latch. The second circuit means also couples data from the cache to the first-in-first-out memory in the event of a cache hit. Finally, a bus control means is provided for controlling the orderly flow of data in accordance with the architecture of the microprocessor. Large, infrequently used data structures can thus be handled rapidly without disturbing cache-resident data. <IMAGE>