发明名称 |
Microprocessor having improved functional redundancy monitor mode arrangement. |
摘要 |
<p>A plurality of gates are arranged between buffers and a coincidence circuit. The gates are also coupled to terminals by which data is inputted during a monitor mode. An invalid byte information generator is connected to the gates and applies a signal selected to mask the effects of write instructions being executed on a incomplete word and therefore prevents the generation of an erroneous mismatch signal.</p> |
申请公布号 |
EP0382234(A2) |
申请公布日期 |
1990.08.16 |
申请号 |
EP19900102566 |
申请日期 |
1990.02.09 |
申请人 |
NEC CORPORATION |
发明人 |
KOUMOTO, YASUHIKO;MAEMURA, KOJI |
分类号 |
G06F11/18;G06F11/00;G06F11/16 |
主分类号 |
G06F11/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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