| 摘要 |
This invention relates to an LSI in which a gate electrode wiring in a logic cell which is constructed by combining a plurality of basic cells each of which consisting of a pair of p-type and n-type MOS transistors and a gate electrode wiring, has portion extending substantially to a marginal region which does not contain logic cells. Additionally wiring portions associated with the LSI are disposed in a layer different from the layer to which the extended portions of the gate electrode wiring belongs. The extended portions, in the marginal region, are connectible portions through through holes. Such a structural arrangement results in an increase in the gate utilization ratio and improves the reliability of an LSI without decreasing the freedom to lead the wiring between gates.
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