| 摘要 |
<p>PURPOSE:To simplify a system by deviating the timing of the read of a data from an elastic memory capable of the correction of delay in response to the output of an error counter. CONSTITUTION:The timing of the delay of a received signal due to a difference from a signal series, dispersion in the line quality and fading or the like is deviated by the output of an error counter 12 at the speed conversion of a speed conversion circuit 10. The error counter 12 counts an error signal outputted from a reception signal processing circuit 11 receiving the output of the speed conversion circuit 10. Thus, the timing at the speed conversion is shifted by the output of the error counter 12 to correct the delay in the received signal simultaneously, thereby simplifying the system.</p> |
