发明名称 STRUCTURED LOGIC ARRAY
摘要 A first logic array has a set of input lines for receiving the binary input signals. A second logic array has a set of output lines on which the binary output signals emanate. A first set of intermediate word-lines emanate from the first array. A second set of word-lines, operably connected to the first set of intermediate word-lines, enter into the second array. A combinational logic element responds to binary signals emanating from the first logic array on the first set of word-lines and processes the binary signals so that the programmed logic array can implement at ELSE statement.
申请公布号 KR900005791(B1) 申请公布日期 1990.08.11
申请号 KR19820003653 申请日期 1982.08.14
申请人 WESTERN ELECTRIC CO., LTD. 发明人 HARRISON MARK L.
分类号 H03K19/177;(IPC1-7):H03K19/096 主分类号 H03K19/177
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