| 摘要 |
PURPOSE:To contrive the improvement of the integration degree of an element by a method wherein first and second contact parts are respectively provided on first and second power conductors and source regions are formed in a region to reach from the position of the first or second contact part to a poly silicon wiring according to date to program. CONSTITUTION:SDG regions 8 and 11 are formed on a path to reach from the positions of contact parts 5 and 6 to the position of a contact part 7 according to data to program. That is, at these regions 8 and 11, N-type diffused layers 9 and 12, which are used as source regions, are formed in a region to reach from the positions of the contact parts 5 and 6 to a poly silicon wiring 4, N-type diffused layers 10 and 13, which are used as drain regions, are formed in a region to reach from the position of the contact part 7 to the wiring 4 and the region between both diffused regions is used as a channel region. Accordingly, e=a memory cell transistor can be miniaturized by the amount of a. dimension reducible in the direction of the word line 4. Thereby, the improvement of the integration degree of an element is contrived. |
