| 摘要 |
PURPOSE:To prevent a malfunction by the superposition of clocks due to the load capacity or resistance of output wiring, or the lowering of the maximum operating frequency due to excessive delay width between the clocks occurring by varying delay time by a control signal. CONSTITUTION:P-type MOSFETs M1 and M2, and N-type MOSFETs M5 and M6 with different dimension (W/L) are provided, and the relation of respective dimension is assumed as M1>M2 and M5>M6, respectively. When a level is set at an 'H' level, the P-type MOSFET M1 and the N-type MOSFET M5 are turned on, and when it is an 'L' level, the P-type MOSFET M2 and the N-type MOSFET M6 are turned on. Therefore, the P-type MOSFETs M1 and M2 and the N-type MOSFETs M5 and M6 with different dimension are switched by controlling the inverter consisting of a P-type MOSFET M3 and an N-type MOSFET M4 by the control signal (c), and rise time and fall time cam be varied, which can adjust the delay time. In such a manner, the superposition occurs in the minimum delay time, which can dissolve the defect of the malfunction. |
