| 摘要 |
<p>PURPOSE:To reduce power consumption and to effectively operate an internal circuit by using a frequency-dividing output signal selected in a selection circuit as the operation timing signal of a circuit in an integrated circuit and an internal program storage device. CONSTITUTION:A frequency-dividing value D1 for the internal PG storage device 6 is stored in a frequency-dividing register 11 in a programmable clock frequency divider 4a by a frequency-dividing value write instruction I stored in an internal program (PG) memory area, and a frequency-dividing circuit 10 controls the value D1. An original clock (CL) signal generated in an original clock generation circuit 3 is frequency-divided, and outputted to a basic clock selection circuit 8 as a CL signal phi1. At the same time, a frequency-dividing value D2 for a storage device 2 is stored in the register 11 in the frequency divider 4 by the instruction I, the circuit 10 is controlled in accordance with the value D2 and outputted to the circuit 8 as a CL signal phi2. The circuit 8 selects signals phi1 and phi2 in accordance with a control signal CLT from a NOR circuit 13, and inputs them to the internal circuit 7. The selection circuit 12 selects the signals phi1 and phi2 in accordance with the signal CNT and sets them to a register 9.</p> |
