| 摘要 |
PURPOSE:To prevent the deterioration in the gate availability and to attain the satisfactory cost performance by using 2 types or more of basic cells to form a logic circuit. CONSTITUTION:In case a circuit is formed in a programmable logic element PLD 10 including three pieces (C1-C3) of basic cells 12A only, the gates N1, E1, O1 and FFF1 are formed at a programmable combinational logic circuit PCL 22 and an FF 24 of the first basic cell C1. Then a 2nd FFF2 and a 3rd FFF3 are formed at the FF 24 and the FF 24 of the second and third cells C2 and C3 respectively. In this case, the PCLs 22 of the cells C2 and C3 are not used and useless. In case the same circuit is formed in a PLD including a piece (C4) of cell 12A and two pieces (C5, D6) of basic cells 12B, the gates N1, E1, O1 and FFF1 are formed at the PCL 22 and the FF 24 of the cell C4. Then an FFF2 and an F3 are formed at an FF 34 and an FF 36 of a basic cell C5. The cell C5 is not required. |
