| 摘要 |
A CEPT transceiver (115, 125) wherein a serial control port (130) permits close microprocessor-based control. A RAM-based architecture (140) is used for the control and status registers, with access restrictions on the serial port (130) side to prevent access collisions. The transmit and receive clocks (110, 120) are allowed to be totally asynchronous to the serial port's clock, and no status updates are ever missed. |
