发明名称 MEMORY READ CIRCUIT
摘要 <p>PURPOSE:To obtain a sure and highly reliable memory read circuit by providing a level comparing circuit, which inputs the respective outputs of a pseudo memory and a memory to second and first circuits in the same configuration, responds to respective output signals, and outputs a read signal corresponding to read contents. CONSTITUTION:A first output circuit 7 produces a first output signal having either one of first or second level according to the read contents of a necessary memory 2, on the other hand a second output circuit 13 produces a second output signal in response to a reference signal from a pseudo memory 14. Further the first output signal 13 is level-compared with the second output signal, and based on a level comparison result, the read signal is outputted. The configurations of the second circuit and the first circuit 7 are perfectly the same, the stable operation can be executed, and a malfunction due to a noise is hardly generated. Thus a sure and highly reliable memory read circuit 1 can be obtained.</p>
申请公布号 JPH02201799(A) 申请公布日期 1990.08.09
申请号 JP19890021625 申请日期 1989.01.31
申请人 SEIKO INSTR INC 发明人 KOBAYASHI KENICHI
分类号 G11C17/00;G11C16/06 主分类号 G11C17/00
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