| 摘要 |
PURPOSE:To efficiently use a first in first out (FIFO) buffer for data by setting data to a register at the time of knowing that this data is repeated in firmware. CONSTITUTION:Data to be compressed is preliminarily written in the register of a load control circuit 20 from firmware. When input data of an input data bus IDB is equal to data written in the register and is repeated, a data load signal DL is stopped by a load control circuit 20 not to load input data to a FIFO buffer 10 for data. A second control signal C2 is used to indicate suppression of unload to an unload control circuit 30. Thus, the FIFO buffer is efficiently used. |
