发明名称 IMPROVED DETERMINISTIC TIMED BUS ACCESS METHOD
摘要 <p>An improved timed deterministic bus access method and system is described which can be used with a bidirectional linear bus, a uni-directional linear bus, a star and a tree type of bus structure. The method employs a master timing reference signal and discrete values of time delay at each node together with a cycle start signal to provide orderly deterministic access by a number of nodes to a shared bus structure. The master timing reference signal is generated by a polling node which can also transmit messages. The time delays in the nodes can correspond to their physical order from the polling node when this is located at one end. Alternatively values of timing delays can be chosen to make the physical location of the polling node or the other nodes unimportant. The method provides for prioritised access to the bus structure using a reservation hold.</p>
申请公布号 WO1990009068(A1) 申请公布日期 1990.08.09
申请号 GB1990000147 申请日期 1990.02.01
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