| 摘要 |
<p>PURPOSE:To improve the yield in promoting the degree of integration of a whole chip by selecting either data from a 1st storage part or a 2nd storage part to be outputted, separating and arranging the 1st and 2nd storage parts from each other. CONSTITUTION:When a defective cell is found in a mask ROM cell array 16 of the 1st storage part 18, a redundant address showing this defective cell is set in a redundancy deciding circuit 13, and moreover the same data as a data to be written in a cell with a capacity of one row including the defective cell is written by a write control circuit 19 to a PROM cell array 23. Then, when an inputted address signal is conformed with the redundant address, a data of the side of the 2nd storage part 24 is selected by a selection circuit 25 to be outputted. Consequently, the 1st storage part 18 and the 2nd storage part 24 are separately arranged, and neither word lines nor bit lines are shared at all. By this method, a defective can be relieved by the storage part 24 while the degree of integration of the 1st storage part 18 is insured, and the yield is thus improved.</p> |
