Self timed register file.

摘要

In very high speed computers, the duration of time required for the system clock signal to travel to various components of the computer becomes critical. In these high speed computers the frequency of the clock signal is very fast with a resultant decrease in the clock period. Accordingly, the clock skew or travel time becomes significant as compared to the shortened clock period. An operation, intended to be synchronous with the clock pulse, actually occurs a predetermined time later, equivalent to the clock skew. This asynchronous operation can result in unstable data being stored in the CPU registers. A self timed register (STREG) 44 is constructed on a single custom ECL integrated circuit and has provisions for generating its own internal clock signal. The STREG 44 includes a set of latches 80a-80q for temporarily storing the data delivered thereto concurrent with the system clock pulse. Thereafter, the internally generated clock pulse (WPULS) controls the write operation of the temporary latches into the STREG 44.