Bi-MOS logic circuit having a switch circuit for discharging electrical charge accumulated in a parasitic capacitor.

摘要

Disclosed herein is a Bi-MOS logic circuit comprising first and second NPN transistors (Q11, Q12) forming an output buffer; first and second MOS transistors (N11, N12) for controlling the NPN transistors (Q11, Q12) when the logic circuit is set to a data-latching mode; and third and fourth MOS transistors (N13, N14) for controlling the NPN transistors (Q11, Q12) when the logic circuit is set to a data-inputting mode. The Bi-MOS logic circuit further comprises a switch circuit (SW) for discharging a parasitic capacitor (C) located at the node of the series circuit comprised of the first and second MOS transistors (N11, N12).