发明名称 |
Semiconductor memory device having mask rom structure. |
摘要 |
<p>A semiconductor memory device includes a memory cell array (10) having a plurality of memory cells (MC) and formed by a mask ROM, the memory cell array having a data area (10a) in which data (SO1 - SO16) of n bits (n is an arbitrary number) is stored and a parity area (10b) in which a one-bit parity code (Pb) relating to the data is stored. A control circuit (13, 14) supplies the memory cell array with an address and reads out the data and the one-bit parity code designated by the address. A parity check circuit (16) determines whether or not the data read out from the memory cell array has a bit error and generates correction data (CB) indicating a determination result. A memory (17) stores defective output indicating data (S1 - S16) indicating one of the n bits of the data having the bit error. A data correction circuit (15) corrects one of the n bits of the data indicated by the defective output indicating data by the correction bit.</p> |
申请公布号 |
EP0381405(A1) |
申请公布日期 |
1990.08.08 |
申请号 |
EP19900300881 |
申请日期 |
1990.01.29 |
申请人 |
FUJITSU LIMITED;FUJITSU VLSI LIMITED |
发明人 |
ARAKI, SUNAO |
分类号 |
G11C17/00;G06F11/10;G06F11/22;G11C17/12;G11C29/00;G11C29/42 |
主分类号 |
G11C17/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|