发明名称 |
Latch-up resistant CMOS structure |
摘要 |
A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolated N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.
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申请公布号 |
US4947227(A) |
申请公布日期 |
1990.08.07 |
申请号 |
US19850776553 |
申请日期 |
1985.09.16 |
申请人 |
TEXAS INSTRUMENTS, INCORPORATED |
发明人 |
TENG, CLARENCE W. |
分类号 |
H01L27/08;H01L21/762;H01L21/8234;H01L27/088;H01L27/092 |
主分类号 |
H01L27/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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