发明名称 CIRCUIT FOR SUM OF PRODUCTS
摘要 PURPOSE:To remove a coding circuit, to reduce the number of elements and to contract the area of a chip by providing the circuit for sum of products with an integration control circuit for reversing the connection of a capacitor to an operational amplifier in a mirror integrating circuit in accordance with positive or negative expressed by a weight code. CONSTITUTION:Exclusive OR circuits 54, 55 form a control signal CONT and the inverse of CONT respectively from a code and an offset cancel (OC) signal and output respective signals through OR circuits 50, 51. When a code from an FF 45 is positive, only analog switches SW1, 4 are connected in a signal integration holding period, and in the case of an offset integration holding period, only switches SW2, 3 are connected. When the code is negative on the contrary, only the switches SW2, 3 are connected in the signal integration holding period, and only the switches SW1, 4 are connected in the offset integration holding period. Consequently, the connection of the capacitor CT to the operational amplifier 19 in the signal and offset integration holding periods are respectively reversed in accordance with the positive and negative of the code and a prescribed signal is outputted from a terminal 20.
申请公布号 JPH02199592(A) 申请公布日期 1990.08.07
申请号 JP19890020296 申请日期 1989.01.30
申请人 FUJITSU LTD 发明人 ISHIKAWA KATSUYA;TSUCHIYA CHIKARA;IWAMOTO HIROSHI;SUGIURA YOSHIHIDE;YOSHIZAWA HIDEKI;ICHIKI HIROMOTO;KATO HIDEKI;ASAKAWA KAZUO;TSUZUKI HIROYUKI;ENDO SHUICHI;KAWASAKI TAKASHI;MATSUDA TOSHIHARU
分类号 G06G7/14 主分类号 G06G7/14
代理机构 代理人
主权项
地址