发明名称 PARALLEL LOGIC SIMULATION SYSTEM
摘要 PURPOSE:To reduce the volume of a message and that of processing and to speed up simulation by transmitting a dead lock message to which the final time at which an output value is not changed inspite of a change in an input to a gate is applied as a reset time and advancing pin time up to the reset time when the message is returned. CONSTITUTION:A dead lock message(DLM) transmitting part 1 generates and transmits a DLM to which the final time at which its output value is not changed inspite of a change in the input is added and a DLM receiving/ propagating part 2 receiving the DLM updates the reset time added to the DLM, transmits the updated DLM, and when the DLM is returned, the pin time is advanced up to the reset time. Consequently, the volume of a message and the volume of processing in a processor can be reduced and simulation can be rapidly executed.
申请公布号 JPH02199547(A) 申请公布日期 1990.08.07
申请号 JP19890020263 申请日期 1989.01.30
申请人 FUJITSU LTD 发明人 SHIMOGOORI SHINTARO;KAGE TETSUO
分类号 G06F11/25;G06F11/26;G06F17/50;G06F19/00 主分类号 G06F11/25
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