STRUCTURE FOR A LATCHUP ROBUST GATE ARRAY USING THROUGH WAFER VIA

摘要

A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.