Method and circuit for testing integrated circuit modules

摘要

A method and circuit for identifying hidden faults in the internal circuit parts of integrated CML-logic-circuits include reducing the voltage difference between the high and low binary signals (logic swing) during testing so that the noise immunity is diminished. The logic swing is reduced by varying reference voltages for constant current sources and differential amplifiers through the use of an integrated control circuit connected to influence reference voltage generators. The control circuit is activated by reducing the supply voltage in a first embodiment or, in a second embodiment, by an external control signal.