发明名称 PROGRAMMABLE LOGIC ARRAY
摘要 PURPOSE:To quickly attain the test of an FF by providing a deciding circuit, which decides the coincidence between the non-inverted output and the inverted output of the flip-flop(FF) on an output stage, and a circuit, which selectively fetches one output of the FF and the output of the deciding circuit. CONSTITUTION:An FF 2 is provided on the output stage of a programmable logic array(PLA) 1. A deciding circuit 3 decides whether or not the non-inverted output of the FF 2 corresponds to the inverted output. An output selecting circuit 4 selectively fetches one output of the FF 2 and the output of the circuit 3 to an output terminal is response to a control signal. At the time of testing, when the operation of the FF 2 is normal, the output is fetched to the terminal 5, when the operation is abnormal, a signal to indicate the coincidence is fetched to the terminal. Consequently without taking into consideration feedback to an AND array, and regardless of a programmed logical function, whether or not the FF is normally operated can be easily and promptly tested.
申请公布号 JPH02195723(A) 申请公布日期 1990.08.02
申请号 JP19890014735 申请日期 1989.01.24
申请人 FUJITSU LTD 发明人 SAITO HITOSHI
分类号 G06F7/00;H03K19/177 主分类号 G06F7/00
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