Digital signal time base corrector for video tape recorder

摘要

The digital video signals including block synchronisation signals are applied to a phase-locked loop clock generator (1) which addresses a write clock signal (WCL) to a first-in first-out memory (3), where the signals are stored after serial-to-parallel conversion (2). The reference readout clock signal (RCL) is shared by the sync detector (4) and another FIFO memory (6) into which the signals are written with bits rotated (5). This memory (6) delivers the corrected video signal in response to readout pulses (GRZ) from a controller (7).