发明名称 REJISUTASEIGYOKAIRO
摘要 PURPOSE:To leave the result of shift of the content of a register in a single processing unit by making to update the contents of a pointer with an output of an adder, in a register control circuit of a data processor. CONSTITUTION:In storing a data in a register 31, a data is fetched from a bus 36, and the contents of a pointer 33 representing the location of the uppermost order bit of the register 31 is reset by using a reset signal 39. When shifting the contents of the register 31, an external shift constant 37 and the contents of the pointer 33 are added with an adder 34, the result in written in the pointer 33 and inputted to a decoder 35. The decoder 35 decodes the result of the adder 34 and outputs it to a barrel shifter circuit 32 as a shift control signal 38. Further, the contents of the register 31 is inputted to the barrel shifter circuit 32 and outputted on a bus 36 according to the shift control signal 38.
申请公布号 JPH0234053(B2) 申请公布日期 1990.08.01
申请号 JP19820169139 申请日期 1982.09.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 WAKABAYASHI NAOKI;NISHIZAWA TEIJI
分类号 G06F7/00;G06F5/01;G06F7/76;G06F9/315 主分类号 G06F7/00
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