SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PURPOSE:To reduce the interphase skew of the internal clock signals of plural phases, which synchronously operate an ASIC memory, etc., by constituting a clock generation circuit by means of a frequency dividing circuit where a couple of latches are set to be a basic constitution and plural differentiation circuits which receive the output signals of the frequency-dividing circuit. CONSTITUTION:The internal clock signals of plural phases, which are required in the ASIC(Application Specific Integrated Circuits) memory, etc., are formed based on the basic clock signal of one phase, which is supplied from outside. The clock generation circuit provided on the ASIC memory, etc., is constituted by the frequency dividing circuit FD1 where a couple of latches LT1 and LT2 are set to be basic constitution, and by plural differentiation circuits DCP1, DCP2 DCN1 and DCN2, which receive the output signals of the frequency dividing circuit FD1. Thus, the internal clock signals of plural phases can stably be formed without being affected by the external skew, and the interphase skew is considerably reduced.