| 摘要 |
PURPOSE:To automatically and speedily put a PLL circuit in the locked state even if the PLL circuit is unlocked by switching a counted value to be decided as a synchronizing signal when the PLL circuit is in the unlocked state and enabling synchronous detection. CONSTITUTION:When the PLL is unlocked, the specific value of a detecting circuit 23 is switched selectively to other predetermined values, e.g. '3' and '7'. The specific value is put back to the original value (e.g. '5') after the synchronizing signal is obtained correctly and the PLL3 corrects the frequency of a clock almost to a target accordingly. Namely, when the PLL is unlocked, the switching of the specific values in the order of (b) (e.g. b=3) (a) (e.g. a=5), and (c) (e.g. c=7) (a) is carried on periodically until the PLL enters the locked state. Consequently, even if the PLL is unlocked temporarily, the PLL can be put in the PLL locked state speedily as long as the correct received signal is obtained and the correct clock extraction is possible, so biphase demodulation can be performed by using this clock. |
