| 摘要 |
<p>PURPOSE:To obtain an IC in which phase difference between clocks at every part is eliminated and which can be operated with high reliability at high speed by setting resistance and capacitance at the connecting terminal of each wiring to each load so as to be equal with each other at every connecting terminal, and attaching a resistor and a capacitor at need. CONSTITUTION:Amplifiers A1 and A2 are provided with the same driving capacity, and when different values are attached on load gates G1-G5, the capacitors C1-C3 are attached so that the load capacitance of the gate G1 can be set equally to the capacitor C1, and that of the gate G2 can be set equally to the capacitor C2, and the capacitance of the gate G3 and that of the capacitor C3 can be set equally to the capacitance of the gates G4 and G5, respectively, and also, wiring resistors R1 and R2, and resistors R3 and R4 can be set equally, respectively. Thereby, two-phase clocks phi1 and phi2 generate attenuation and delay equally at every part. Also, both wiring resistance and capacitance can be set equally by wiring with the clocks phi1 and phi2 of same width and length. By comprising a circuit in such way, the IC in which no phase difference occurs among multi- phase clocks at every point in the circuit can be obtained, which realizes the high reliability and a fast operation.</p> |
