SPEED - UP CIRCUIT FOR MICRO PRECESSOR

摘要

The circuit comprises a flip-flop FF disabling an operation of microprocessor by a reset signal; a branch circuit FD branching the system clock by the reset signal; a counter CTR enabled by the low level output signal of the flip-flop; a ROM enabled by oscillation signal from the monostable multivibrator MM; a RAM controlled by outputs of gates G4, G5 and enabled by output of gate G6, in which the reading data of ROM is written; a buffer BFI connected to the data bus and controlling the data transmission between the ROM and the RAM; and buffer BF2 connected to the address bus of the system and controlling the data transmission to the ROM ad RAM.