| 摘要 |
The bus system for decoding the data and address communcating between a CPU of main system and the peripheral apparatus comprises a bus buffer (10) determining the data transmission direction with a data read signal, a flip-flop (20) synchronised by a logical multiplied signal by an address (Ao) of LSB and data write signal, a buffer (30) enabled by the data read signal decoders (40,41) providing 16 bit decoding signal, an address decoder (50) providing a selection signal, and bus buffers (11,12) enabled by OR gate (G1-2) output signals and the data read signals.
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