发明名称 GATE ARRAY TYPE SEMICONDUCTOR DEVICE
摘要 PURPOSE:To make it possible to form many basic cells on one chip in the limit of manufacture of the dimension of the chip by a method wherein peripheral circuit chips, which are respectively constituted of each peripheral circuit comprising a static breakdown strength protective circuit, a latch-up protective circuit, an output transistor and the like, and an internal circuit chip comprising basic cells other than the above circuits, transistor and the like are connected to each other on a package. CONSTITUTION:A P-channel output transistor, an N-channel output transistor and a latch-up protective circuit are contained in respective peripheral circuit cells 501. Static protective circuits are respectively constituted of part of the respective output transistors and peripheral circuit chips 5 are provided arranging a necessary number of the cells 501 on each one side. An internal circuit chip 4 and the chips 5 are conformed to lead patterns 1 and peripheral internal patterns (wirings) 2 and are mounted on a package main body 3 in such a way that pads face downward to make the leads 1 and pads 502 and pads 503 and the wirings 2 correspond to each other to connect. Moreover, a power conductor 6 and pads 504 and a grounding conductor 7 and pads 505 are connected to each other to feed a power supply to the chips 5. Thereby, an internal circuit region is made wide within the limited dimension of a chip and the improvement of an integration degree can be attained.
申请公布号 JPH02192144(A) 申请公布日期 1990.07.27
申请号 JP19890011302 申请日期 1989.01.20
申请人 NEC CORP 发明人 KUME TORU
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
代理机构 代理人
主权项
地址